Conclusion

A system for real-time monitoring of energy utilization, which uses an existing internet protocol (IP) network and latest technologies in application specific integrated circuits (ASICs) for energy processing, allowing for a centralized collection of data coming from remotely located sensors has been developed. The system consists of several sensor nodes connected to an IP network and one control computer called the base node.

The sensor node is a stand-alone device capable of collecting, measuring, and transferring electrical information to the central computer. It consists of three modules namely: ASIC Module, MCU Module, and NIC Module. The NIC Module is responsible for network communication and the ASIC Module is responsible for data collection and processing. The MCU Module contains a low level firmware which controls the operation and data transfer between the ASIC and NIC Modules.

During prototype evaluation, the system proves its stability over its range of operation. The power measurement accuracy of the sensor node reaches up to about 98% on its operating range which is 220V ±20% and 5A to 200A. Energy accumulation accuracy declined to about 90% due to ineffective data transmission to the base node. However, the system can be used satisfactorily for monitoring energy utilization.

             Several design iterations has been made until the sensor node was able to make good measurements. One of the design flaw encountered was the audio transformer used to isolating the electrical side from the sensor node electronics. The audio transformer causes unpredictable phase shift at different load conditions that made active power measurements inaccurate. Another was the lack of decoupling capacitors on the supply pins of the operational amplifier used to convert single ended signal from the transducer to differential signal needed by the energy metering chip. The stalling issue of the sensor node at random time interval during its operation is due to lack of noise immunity. It can be resolved by adding a watchdog timer in the algorithm.  Further printed circuit board (PCB) layout techniques must be considered during PCB fabrication to reduce noise affecting the energy processor. A minor operational issue of the ADE7758 was discovered in this research. According to the ADE7758 technical specifications for the SPI bus clock, the maximum clock rate is 5 MHz; at this clock rate consecutive AVRMS and AIRMS register readings would produce a byte swap on their high byte positions. However, at SPI bus clock of 312.5 kHz the readings are normal. Analog Devices technical support team is still on the process of investigating this dilemma.